VHDL/ Verilog Programing Trainee

Kathmandu, Nepal

Responsibilities

  • Working on a live project

  • Following clean code principles and test-driven development

  • Learning to lead and work with a professional team
  • ¬†Improving the quality of one's work

  • Learning to set and meet expectations

Requirements

  • Computer/Electronics Engineering Graduates or Final year students

  • Good Knowledge of C/C++

  • Experience in working with Xilinx Vivado SDK will be an added advantage

  • Knowledgeable and confident in writing, testing, and debugging low-level code (microcontrollers/FPGA)

  • Love to work in a collaborative environment
  • Good leadership skills with self-learning capabilities

  • Good written & verbal communication skills

  • Energetic and eager to tackle new projects and ideas
  • Professional presence is required

What's great in the job?

  • Great team of smart people, in a friendly and open culture

  • Work from home during this pandemic, Monday To Friday

  • Health and Medical Insurance

  • Other fringe benefits


Deadline

20th June, 2021